This invention pertains in general to digital adder circuits and in particular to an adder for binary or binary coded decimal operands.
In digital computers, addition is one of the most fundamental operations and the wide spread development of various types of digital computers has correspondingly resulted in the development of a wide variety of circuits and techniques for performing addition. Since most digital computers function by manipulating data and instructions expressed as binary numbers, most digital logic and circuit developments relating to addition concern the addition of binary numbers. As is well known, the speed with which binary operands can be added is primarily determined by the speed with which carries generated by the addition of individual binary digits can be propagated. Various techniques and circuits for reducing this carry propagation delay time have been developed. The most widely used method for high speed binary addition is commonly referred to as look ahead carry addition. The basic principle of look ahead carry addition is the examination of a number of inputs to each adder stage and the simultaneous production of the proper carries for each of these stages. The application of the carries to the adder block for each stage then produces the proper sum bits. Depending upon the number of look ahead carry levels, the overall add time can be significantly reduced. Although the digital circuitry used in computers make the binary representation of numbers and binary arithmetic the most straightforward approach to solving arithmetic problems, human interface requirements often dictate the use of decimal representation of numbers. Thus, most modern computers provide a capability of operating with both binary numbers and coded decimal numbers such as binary coded decimal (BCD). At low speeds, arithmetic operations involving BCD numbers can be performed with the same hardware which is used to perform binary arithmetic by using software algorithms. If computing speed requirements preclude the use of software algorithms, special digital circuits particularly adapted to BCD arithmetic must be used. One such technique which uses digital circuits specifically designed to perform only BCD arithmetic is described in the paper "High Speed Decimal Addition" by Schmoockler and Weinberger published in the IEEE Transactions on Computers, Volume C20, Number 8, August, 1971. Although this approach gives high speed addition capability for BCD numbers, it requires circuitry that is dedicated only for this purpose and therefore implies additional cost in machines which must also perform binary operations.
Another approach to the problem of BCD addition is to perform addition on the BCD operands as though they were binary numbers to form an intermediate result and then correcting this result to form the correct BCD digit of the sum. The usual method for correcting the intermediate result is to add binary 6. The basis for this method is explained in the textbook "Arithmetic Operations in Digital Computers" by R. K. Richards, D. Van Nostrand Co., Inc., Princeton, N.J., 1955 pp 210-211. Although this approach offers circuit advantages relating to the fact that portions of the logic circuits required for binary arithmetic operations can also be used for BCD arithmetic, it has limitations with respect to speed. These limitations arise because the time required to add the BCD operands to form an intermediate result depends upon the carry propagation delay time. The total time required to obtain the correct BCD representation of the sum thus includes the time required to form the intermediate result and the time required to apply the BCD correction factor so that BCD addition is inherently slower than binary addition.